RFPL: Reliable Field Programmable Logic
The main objective of this workshop is to exchange information related to new techniques that enhance FPGA reliability through Single Event Upset (SEU) mitigation and in-circuit debug. The workshop will investigate the use of novel architectures and techniques for FPGA verification, fault tolerance and debug. This workshop can be of interest for verification and debugging experts that wish to share results about new techniques on fault mitigation and in-circuit debug.
The workshop presentations will be uploaded on the workshop's website shortly.
For questions email at: firstname.lastname@example.org.
- Thu, Sept. 7
- 9:00 - 12:30
- More information