Intel Hardware Accelerator Research Program - A Tutorial for learning and using the Intel® Xeon® with in-package FPGA
This full day tutorial will provide an overview on how to program the Intel® Xeon® with In-package FPGA. This reconfigurable hardware has an integrated host processor with memory coherency between the Intel® Xeon® processor and the FPGA providing a heterogeneous compute solution for workload optimizations. It is proving greater performance and efficiencies across many data center type workloads such as cloud services, analytics, genomics, security, packet processing, virtual switching, compression, deduplication and many more. With a simplified programming model (support for virtual addressing and data caching) the Intel Xeon with integrated FPGA enables new classes of algorithms for acceleration.
The tutorial will also highlight Intel’s Hardware Acceleration Research Program which provides faculty and researchers access to pre-production Intel® Xeon® with integrated FPGA systems and is spurring research in programming tools, operating systems, and innovative applications for accelerator-based computing systems.
During the session the hardware and software architecture will be explained as well as how it can be programmed using RTL and OpenCL. A multi-hour hands-on lab session will be held to allow attendees to get first-hand experience on this exciting new technology.
List of Topics to be covered, including format (e.g. talks, demos, etc), target audience, and pre-requisite knowledge:
- Intel® Xeon® with in-package FPGA hardware and software architecture overview
- Accelerator abstraction layer overview
- Core Cache Interface overview and Accelerator Function Unit design
- Memory Protocol Factory overview
- OpenCL programming
- Hands-on Labs for RTL
Pre-Requisite: basic knowledge of computer logic design and FPGA fundamentals.
Please bring your laptop for the hands-on lab.
- Fri, Sept. 8
- 9:00 - 17:30