Session 1b: Reconfigurable platforms and systems
Track: Paper track
Session chair: Walter Stechele
Full Papers
- 11:00: Enabling Partial Reconfiguration and Low Latency Routing using Segmented FPGA NoCs // Kizheppatt Vipin, Jan Gray and Nachiket Kapre; Mahindra Ecole Centrale, Gray Research LLC, University of Waterloo
- 11:25: Rapid Implementation of a Partially Reconfigurable Video System with PYNQ // Brad Hutchings and Michael Wirthlin; Brigham Young University
- 11:50: Exploring the Potential of Reconfigurable Platforms for Order Book Update // Conghui He, Haohuan Fu, Wayne Luk, Weijia Li and Guangwen Yang; Tsinghua University, Imperial College
Poster Papers
- 12:15: A Partial Reconfiguration based Microphone Array Network Emulator // Bruno da Silva, Federico Dominguez, An Braeken and Abdellah Touhafi; Vrije Universiteit Brussel, Escuela Superior Politecnica del Litoral (ESPOL)
- 12:20: A Dynamic Partial Reconfigurable Overlay Concept for PYNQ // Benedikt Janßen, Pascal Zimprich and Michael Hübner; Ruhr-University Bochum
- 12:25: Body Bias Optimization for Variable Pipelined CGRA // Takuya Kojima, Naoki Ando, Hayate Okuhara, Nguyen Anh Vu Doan and Hideharu Amano; Keio University
- Mon, Sept. 4
- 11:00 - 12:30