Session 3a: Exploiting FPGAs for deep learning
Track: Paper track
Session chair: Deming Chen
Full Papers
- 11:30: Customised Pearlmutter Propagation: A Hardware Architecture for Trust Region Policy Optimisation // Shengjia Shao and Wayne Luk; Imperial College London
- 11:55: Scalable Inference of Decision Tree Ensembles: Flexible Design for CPU-FPGA Platforms // Muhsen Owaida, Hantian Zhang, Ce Zhang and Gustavo Alonso; ETH Zurich
Poster Papers
- 12:20: Parallel Dot-Products for Deep Learning on FPGA // Mário Véstias, Rui Duarte, Horácio Neto and José Sousa; INESC-ID/ISEL/IPL
- 12:25: Leveraging PVT-Margins in Design Space Exploration for FPGA-based CNN Accelerators // Weina Lu, Wenyan Lu, Jing Ye, Yu Hu and Xiaowei Li; Institute of Computing Technology, Chinese Academy of Sciences
- Tue, Sept. 5
- 11:30 - 12:30