Session 5c: Many different FPGA applications

Full Papers

• 10:45: An Implementation method of Poisson Image Editing on FPGA // Ryouhei Maeda and Tsutomu Maruyama; University of Tsukuba
• 11:10: Bridging High-Level Synthesis and Application-Specific Arithmetic: The Case Study of Floating-Point Summations // Yohann Uguen, Florent de Dinechin and Steven Derrien; University Lyon, INSA Lyon, Inria, CITI, University of Rennes 1/IRISA
• 11:35: Flexible FPGA design for FDTD using OpenCL // Tobias Kenter, Jens Förstner and Christian Plessl; Paderborn University

Poster Papers

• 12:00: FPGA Acceleration of the Scoring Process of X!TANDEM for Protein Identification // Jin Qiu, Ping Kang, Li DIng, Yipeng Yuan, Wenbo Yin and Lingli Wang; Fudan University
• 12:05: Accelerating In-System FPGA Debug of High-Level Synthesis Circuits using Incremental Compilation Techniques // Pavan Kumar Bussa, Jeffrey Goeders and Steve Wilton; The University of British Columbia, Brigham Young University
• 12:10: A novel FPGA-based track reconstruction approach for the Level-1 trigger of the CMS experiment at CERN // Robin Aggleton, Luis Ardila-Perez, Fionn Ball, Matthias Balzer, Jim Brooke, Michele Caselle, Luigi Calligaris, Davide Cieri, Emyr Clement, Geoff Hall, Kristian Harder, Peter Hobson, Gregory Iles, Thomas James, Konstantinos Manolopoulos, Takashi Matsushita, Alexander Morton, Dave Newbold, Sudarshan Paramesvaran, Mark Pesaresi, Ivan Reid, Andrew Rose, Oliver Sander, Claire Shepherd-Themistocleous, Antoni Shtipliyski, Thomas Schuh, Sioni Summers, Alex Tapper, Ian Tomalin, Kirika Uchida, Paschalis Vichoudis and Marc Weber; University of Bristol, Karlsruhe Institute of Technology, STFC - Rutherford Appleton Laboratory, Imperial College London, Brunel University London, Austrian Academy of Sciences, CERN
• 12:15: BRAM-based Function Reuse as an Alternative to Hardware Accelerators in Soft-Core Processors // Pedro Henrique Exenberger Becker, Anderson Luiz Sartor, Marcelo Brandalero, Tiago Jost, Luigi Carro and Antonio Carlos Schneider Beck; Universidade Federal do Rio Grande do Sul (UFRGS)
• 12:20: Making a Case for an ARM Cortex-A9 CPU Interlay Replacing the NEON SIMD Unit // Jose Raul Garcia Ordaz and Dirk Koch; The University of Manchester
• 12:25: Exploration of OpenCL for FPGAs using SDAccel and Comparison to GPUs and Multicore CPUs // Lester Kalms and Diana Goehringer; Ruhr-Universität Bochum, TU Dresden