27th International Conference on Field-Programmable Logic and Applications

Session 2c: Optimization of FPGA designs

Track: Paper track

Session chair: Fabrizio Ferrandi

    Full Papers
    • 13:30: Vivado Design Interface: An Export/Import Capability for Vivado FPGA Designs // Thomas Townsend and Brent Nelson; Brigham Young University
    • 13:55: REAPR: Reconfigurable Engine for Automata Processing // Ted Xie, Vinh Dang, Jack Wadden, Kevin Skadron and Mircea Stan; University of Virginia
    • 14:20: Find the Real Speed Limit: FPGA CAD for Chip-Specific Application Delay Measurement // Ibrahim Ahmed, Shuze Zhao, Olivier Trescases and Vaughn Betz; University of Toronto
    Poster Papers
    • 14:45: Optimizing Streaming Stencil Time-step Designs via FPGA Floorplanning // Marco Rabozzi, Giuseppe Natale, Biagio Festa, Antonio Miele and Marco D. Santambrogio; Politecnico di Milano
    • 14:50: In-Switch Approximate Processing: Delayed Tasks Management for MapReduce Applications // Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano and Hiroki Matsutani; National Institute of Informatics, Keio University
    • 14:55: A Systematic Approach to Design and Optimise Streaming Applications on FPGA Using High-Level Synthesis // Mohammad Hosseinabady and Jose Nunez-Yanez; University of Bristol
    • Edgar Blanckaert (3.1) @ Het Pand
    • Mon, Sept. 4
    • 13:30 - 15:00