HMC: FPGAs and 3-D Stacked Memory Architectures: The Hybrid Memory Cube

Hybrid Memory Cube (HMC) systems are comprised of a front end Intel processor, a Xilinx Kintex UltraScale FPGA and 4GB of 3-D DRAM stacked memory connected through two 8-lane links. The HMC architecture is an exciting first offering of a class of rapidly evolving systems that integrate new memory hierarchies and technologies close to reconfigurable logic and standard processors to form more energy efficient, customizable and scalable systems for next generation data center and IoT components.

This workshop will provide a venue for researchers and practitioners to present research results, and discuss and share early experiences using Micron's HMC 3-D memory-FPGA architectures. Additional objectives of this workshop are to provide a venue for all interested researchers to learn about 3-D Memory-FPGA computing, develop international collaborative research agendas, and discuss standards and approaches to foster open source sharing within the HMC community. Workshop participants will have the opportunity to engage in discussions as well as provide feedback to Micron on existing tools and platform capabilities as well as effect future directions of architectures for next generation near memory computing systems.